Freescale Semiconductor /MK60DZ10 /ENET /ECR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ECR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESET)RESET 0 (0)ETHEREN 0 (0)MAGICEN 0 (0)SLEEP 0 (0)EN1588 0 (0)DBGEN 0 (STOPEN)STOPEN

SLEEP=0, DBGEN=0, EN1588=0, ETHEREN=0, MAGICEN=0

Description

Ethernet Control Register

Fields

RESET

Ethernet MAC reset

ETHEREN

Ethernet enable

0 (0): Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.

1 (1): MAC is enabled, and reception and transmission are possible.

MAGICEN

Magic packet detection enable

0 (0): Magic detection logic disabled

1 (1): The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

SLEEP

Sleep mode enable

0 (0): Normal operating mode.

1 (1): Sleep mode.

EN1588

EN1588 enable

0 (0): Legacy FEC buffer descriptors and functions enabled.

1 (1): Enhanced frame time-stamping functions enabled.

DBGEN

Debug enable

0 (0): MAC continues operation in debug mode.

1 (1): MAC enters hardware freeze mode when the processor is in debug mode.

STOPEN

STOPEN Signal Control

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